1. Field of the Invention
The present invention relates to the underfilling and encapsulation of semiconductor devices on a carrier substrate. More specifically, the present invention relates to a method of fabricating a semiconductor assembly, wherein the underfill and encapsulation materials may exhibit differing material properties and are formed using stereolithography.
2. State of the Art
Flip-chip style packaging for semiconductor dice is becoming ever more popular. In a flip-chip package, an array or pattern of external conductive elements such as solder bumps, or conductive or conductor-filled epoxy pillars, protrude from the active surface of the semiconductor die for use in mechanically and electrically connecting the semiconductor die to the patterned ends of conductive traces of higher level packaging, such as a carrier substrate.
There is typically a substantial mismatch in the coefficient of thermal expansion (CTE) between the material of the semiconductor die and that of the carrier substrate, such as a printed circuit board or interposer, bearing the conductive traces to which the external conductive elements of the die are bonded. Due to this substantial CTE mismatch, significant stresses develop between the semiconductor die and carrier substrate during normal thermal cycling. Without a strong mechanical attachment of the semiconductor die to the substrate, the die may debond from the carrier substrate, or one or more of the external conductive elements may fracture or release from its corresponding conductive trace. In addition, the small spacing or pitch of the external conductive elements creates a significant potential for shorting between adjacent conductive elements or conductive elements and adjacent carrier substrate traces due to the presence of a dust particle or condensed moisture between the semiconductor die and the carrier substrate. Therefore, when a flip-chip type of electronic device, such as a semiconductor die, is conductively attached to a carrier substrate, underfilling the space between the device and substrate with an electrically insulative material is very desirable to enhance the mechanical bond between the die and the carrier substrate and to dielectrically isolate adjacent electrical connections between the die and the carrier substrate.
In the past, underfilling has been achieved using a dielectric, polymeric material that is heated to a temperature sufficient for it to flow. A vacuum source is typically used to draw the heated, viscous, dielectric material to fill the region between the substrate and the semiconductor die. However, effecting adequate removal of air, water vapor, and moisture from between the substrate and the semiconductor die has always been a problem associated with the conventional underfill process. A more controlled and precise manufacturing technique termed “stereolithography,” also known as “layered manufacturing,” has been employed recently to form the underfill and encapsulation region in semiconductor packages.
A representative patent disclosing forming the underfill and encapsulation structures of semiconductor device assemblies using stereolithography, assigned to the current assignee of the present application, is U.S. Pat. No. 6,537,482 to Farnworth (hereinafter “the '482 Farnworth Patent”), the disclosure of which is herein incorporated by reference. As shown in FIG. 1, the '482 Farnworth Patent discloses semiconductor device assembly 40 having an underfill and encapsulation region formed using stereolithography. Semiconductor dice 20 having an active surface 22, back side 18, and lateral sides 24 is illustrated having a flip-chip configuration using a ball grid array (BGA) of external conductive elements 30 bonded to a plurality of conductive bond pads 32 contained on the active surface 22. The external conductive elements 30 are bonded to conductive traces 14 on the face 12 of the carrier substrate 10. An underfill structure 50 is formed of a polymerized material that fills the spaces 34 between each semiconductor die 20 and the carrier substrate 10. An encapsulation region or structure 48 formed of a polymerized material, contiguous with the underfill structure 50, seals and protects each semiconductor die 20. The underfill structure 50 and the encapsulation region 48 are formed by immersing the semiconductor device assembly to a predetermined depth in a bath of a liquid photopolymer resin and subsequently curing it using either a controlled light source, thermal process, or both. The process is repeated as necessary to form the complete semiconductor package as exemplified by the semiconductor device assembly 40 shown in FIG. 1.
While the '482 Farnworth Patent provides a useful method for encapsulating and underfilling a semiconductor die to form a semiconductor package, it is limited to forming the underfill and encapsulation regions from a photopolymerizable material having uniform material properties and formed from conventional photopolymerizable materials. Therefore, it is desirable to develop a method that enables varying the photopolymerizable material used to form the underfill and encapsulation regions of the semiconductor package. Furthermore, it would be desirable to tailor the material properties of the photopolymerizable material used to form the underfill and encapsulation structures in specific regions to reduce the thermal stresses experienced by the semiconductor package in service and enable protection of the semiconductor package from external elements.